RunFein accepts the algorithmic configuration of an existing/new block cipher from the user through a GUI to generate a customized software implementation. This work presents RunFein, a tool for rapid prototyping of a major class of block ciphers, namely product ciphers (including Feistel network and Substitution permutation network-based block ciphers). By emulating its interface, the ASIC can beĪccommodated even before fabrication, thus enabling mixed FPGA/ASICĪcceleration of elliptic curve cryptosystemsīlock ciphers are the most prominent symmetric-key cryptography kernels, serving as fundamental building blocks to many other cryptographic functions.
Furthermore, deployingįPGAs supports integration of an ASIC realisation of the same algorithm, Thus, the correctness for large key sizesĭepends only on the correctness of the generator. It is also advantageous for validation of theĬorrectness of the design as, for small parameter values, the design canīe tested exhaustively. This approachīenefits the design in that it allows one to effortlessly exploit theĪvailable resources on the FPGA for variable requirements of securityĪnd performance. the key size and the multiplier radix - and creates a highly efficientĬustom RTL description which is synthesized into a FPGA. Instead, a generator program accepts the two main parameters Pure RTL-based synthesis is as unsuitable as high-level By their very nature, cryptosystems challenge both design and Prototyping of elliptic curve public-key cryptosystem hardware isĭescribed. A generator-based design and validation methodology for rapid
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